Tesla’s full self-driving (FSD) computer is the world’s first purpose-built computer for the highly demanding workloads of autonomous driving. It is based on a new System on a Chip (SoC) that integrates industry-standard components such as CPUs, ISP, and GPU, together with our custom neural network accelerators. The FSD computer is capable of processing up to 2300 frames per second, a 21× improvement over Tesla’s previous hardware and at a lower cost, and when fully utilized, enables a new level of safety and autonomy on the road.
- Convolution ,
- Autonomous systems ,
- Artificial neural networks ,
- Random access memory ,
- Graphics processing units
THE PRIMARY goal of Tesla’s full self-driving(FSD) computer is to provide a hardware platform for the current and future data processing demands associated with full self-driving. In addition, Tesla’s FSD computer was designed to be retrofitted into any Tesla vehicle made since October 2016. This introduced major constraints on form factor and thermal envelope, in order to fit into older vehicles with limited cooling capabilities.
The heart of the FSD computer is the world’s first purpose-built chip for autonomy. We provide hardware accelerators with 72 TOPs for neural network inference, with utilization exceeding80% for the inception workloads with a batch size of 1. We also include a set of CPUs for control needs, ISP, GPU, and video encoders for various preprocessing and postprocessing needs. All of these are integrated tightly to meet a very aggressive TDP of sub-40-W per chip.
The system includes two instances of the FSDchip that boot independently and run independent operating systems. These two instances also allow independent power supply and sensors that ensure an exceptional level of safety for the system. The computer as shown in figure 1 meets the form, fit, and interface level compatibility with the older hardware.
The FSD chip is a 260-mm2die that has about250 million gates or 6 billion transistors, manufactured in 14-nm FinFet technology by Samsung. As shown in Figure 2, the chip is packaged in a37.5 mm37.5 mm Flip Chip BGA Package. The chip is qualified to AEC-Q100 Grade2 reliability standards. Figure 2(a) shows the major blocks in the chip. We designed the two instances of neural-network accelerator (NNA) from scratch and we chose industry-standard IPs such as A72 CPUs, G71GPU, and ISPs for the rest of the system. The rest of the unmarked area of the chip consists of peripherals, NOC fabrics, and memory interfaces. EachNNA has 32-MB SRAM and9696 MAC array. At 2GHz, each NNA provides36 TOPs, adding up to 72TOPs total for the FSDchip.The FSD SoC, as shown in Figure 2(b), provides general-purpose CPU cores that run most of theautopilotalgorithms. Every few milliseconds, new input frames are received through a dedicated image signal processor where they get pre-processed before being stored in the DRAM. Once new frames are available in the main memory, the CPUs instruct the NNA accelerators to start processing them. The accelerators control the data and parameters streaming into their local SRAM, as well as the results streaming back to the DRAM. Once the corresponding result frames have been sent out to the DRAM, the accelerators trigger an interrupt back to the CPU complex. The GPU is available for any postprocessing tasks that might require algorithms not supported by the NNA accelerators.
Tesla’s FSD Computer provides an exceptional 21performance uplift over commercially available solutions used in our previous hardware while reducing cost, all at a modest25% extra power. This level of performance is achieved by the uncompromising adherence to the design principle we started with. At every step, we maximized the utilization of the available compute bandwidth with a high degree of data reuse and a minimalistic design for the control flow. This FSD Computer will be the foundation for advancing the FSD feature set. The key learning from this work has been the tradeoff between efficiency and flexibility. A custom solution with fixed-function hardware offers the highest efficiency, while fully programmable solutions are more flexible but significantly less efficient. We finally settled on a solution with con-figurablefixed-function hardware that executes the most common functions very efficiently but added a programmable SIMD unit, which executes less-common functions at a lower efficiency. Our knowledge of the Tesla workloads deployed for inference allowed us to make such a trade-off with a high level of confidence.
The Kavian Scientific Research Association (KSRA) is a non-profit research organization to provide research / educational services in December 2013. The members of the community had formed a virtual group on the Viber social network. The core of the Kavian Scientific Association was formed with these members as founders. These individuals, led by Professor Siavosh Kaviani, decided to launch a scientific / research association with an emphasis on education.
KSRA research association, as a non-profit research firm, is committed to providing research services in the field of knowledge. The main beneficiaries of this association are public or private knowledge-based companies, students, researchers, researchers, professors, universities, and industrial and semi-industrial centers around the world.
Our main services Based on Education for all Spectrum people in the world. We want to make an integration between researches and educations. We believe education is the main right of Human beings. So our services should be concentrated on inclusive education.
The KSRA team partners with local under-served communities around the world to improve the access to and quality of knowledge based on education, amplify and augment learning programs where they exist, and create new opportunities for e-learning where traditional education systems are lacking or non-existent.
FULL Paper PDF file:Compute Solution forTesla’s Full Self-DrivingComputer
Compute Solution forTesla’s Full Self-DrivingComputer
n IEEE Micro, vol. 40, no. 2, pp. 25-35, 1 March-April 2020,
PDF reference and original file: Click here
Professor Siavosh Kaviani was born in 1961 in Tehran. He had a professorship. He holds a Ph.D. in Software Engineering from the QL University of Software Development Methodology and an honorary Ph.D. from the University of Chelsea.